Xilinx ISE: адресное пространство для BLOCK ROM и RAM с использованием файла BMM с примитивами RAMB32

Question

Xilinx ISE: адресное пространство для BLOCK ROM и RAM с использованием файла BMM с примитивами RAMB32

Я должен сопоставить ПЗУ с адресом 0x0000 до 0xFFFF и ОЗУ с адресным пространством 0x10000-0x1FFFF. Я сгенерировал следующий оперативной памяти от CoreGen:

component brom_im
 port (
    clka : IN std_logic;
    addra: IN std_logic_VECTOR(15 DOWNTO 0);
    douta: OUT std_logic_VECTOR(31 DOWNTO 0));
end component;

component bram_dm
 port (
    clka: IN std_logic;
    dina: IN std_logic_VECTOR(31 downto 0);
       addra: IN std_logic_VECTOR(15 downto 0);
    wea: IN std_logic_VECTOR(3 downto 0);
    douta: OUT std_logic_VECTOR(31 downto 0));
end component;

для которого я должен написать файл BMM. После места и маршрута я нашел следующие имена экземпляров, используя PlanAhead.

BRAM_instance (bram_dm)

U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[46].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[53].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[59].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[57].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[44].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[47].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[49].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[62].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[45].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[43].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[58].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[48].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[60].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[55].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[50].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[52].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[56].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[51].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[63].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[61].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)

и BROM_instance (brom_im):

U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[50].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[49].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[48].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[48].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[52].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[43].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[47].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[51].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[49].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[45].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[52].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[51].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_B (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[46].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[50].ram.r/v5_init.ram/SP.CASCADED_PRIM36.TDP_T (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[44].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)
U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP)

На основании этих примитивов, как я могу написать правильный файл BMM. Есть 64 линии для BRAM и 52 линии для BROM, какие линии должны использоваться в BMM?
Как использовать так много битовых дорожек для доступа только к 32-битной оперативной памяти?
Как использовать сочетание SINGLE_PRIM36.SP, CASCADED_PRIM36.TDP_T, CASCADED_PRIM36.TDP_B в битовых дорожках для ПЗУ?

Я пробовал следующий файл BMM, но адресное пространство не отображается должным образом.

    ADDRESS_SPACE pr_mem1 RAMB32 [0x00000000:0x0000ffff]
    BUS_BLOCK
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:30];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [29:28];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [27:26];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [25:24];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [23:22];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [21:20];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [19:18];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [17:16];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [15:14];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [13:12];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [11:10];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [9:8];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [7:6];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [5:4];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [3:2];
        BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP  [1:0];
    END_BUS_BLOCK;
END_ADDRESS_SPACE;

ADDRESS_SPACE pr_mem2 RAMB32 [0x00010000:0x0001ffff]
    BUS_BLOCK
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:30];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [29:28];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [27:26];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [25:24];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [23:22];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [21:20];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [19:18];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [17:16];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [15:14];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [13:12];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [11:10];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [9:8];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [7:6];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [5:4];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [3:2];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [1:0];
    END_BUS_BLOCK;
END_ADDRESS_SPACE;

Когда я пытался объединить эти файлы с битовым файлом, используя data2mem, он выдает следующие ошибки:

ERROR:Data2MEM:47 - Not all BitLanes in ADDRESS_SPACE 'pr_mem2' have BMM location constraints.
    Some data for this ADDRESS_SPACE may be lost during BIT file
    replacement. Verify that the BMM file has location constraints
    for all BitLanes.

      Bitlane(s)
   ----------------
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:30]
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [29:28]
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [27:26]
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [25:24]
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [23:22]
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [21:20]
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [19:18]
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [17:16]
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [15:14]
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [13:12]
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [11:10]
   BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [9:8]

Пожалуйста помоги! С уважением

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vhdl fpga xilinx synthesis virtex

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user8581177 25 окт '17 в 00:18

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