Cuando corremos "Generate Programming File" nos marca error pero en la ventana de error no nos indica cual es, ¿Cómo se podrá solucionar este error?
Этот набор кодов xilinx представляет собой дизайн-пакет 14.1 для Nexys 4 с Artix 7, с кодом, который может быть реализован PicoBlaze, функция кодирования кодирования и кодирования 8 светодиодов с соответствующим переключателем, синтезом и реализацией схемы для всех устройств. cabo sin errores solo se obtuvieron предупреждения. El error se describrira mas adelante.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_kcpsm6 is
Port ( clk : in STD_LOGIC;
Leds : out STD_LOGIC_VECTOR (7 downto 0);
sw : in STD_LOGIC_VECTOR (7 downto 0));
end test_kcpsm6;
architecture Behavioral of test_kcpsm6 is
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal bram_enable : std_logic;
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
signal kcpsm6_sleep : std_logic;
signal kcpsm6_reset : std_logic;
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := x"00";
interrupt_vector : std_logic_vector(11 downto 0) := x"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component led
generic( C_FAMILY : string := "7S";
C_RAM_SIZE_KWORDS : integer := 2;
C_JTAG_LOADER_ENABLE : integer := 0);
port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
begin
-- programming of processor
program_rom: led
generic map( C_FAMILY => "7S",
C_RAM_SIZE_KWORDS => 2,
C_JTAG_LOADER_ENABLE => 0)
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => kcpsm6_reset,
clk => clk);
-- processor
processor: kcpsm6
generic map( hwbuild => x"00",
interrupt_vector => x"3FF",
scratch_pad_memory_size => 64)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
sleep => kcpsm6_sleep,
reset => kcpsm6_reset,
clk => clk);
input_ports: process(clk)
begin
if clk'event and clk='1' then
case port_id(0) is
when '0' => in_port <= sw;
when others => in_port <= "XXXXXXXX";
end case;
end if;
end process input_ports;
output_ports: process(clk)
begin
if clk'event and clk='1' then
if write_strobe = '1' then
if port_id(0) = '1' then
Leds <= out_port;
end if;
end if;
end if;
end process output_ports;
end Behavioral;
Aquí esta la asignación de los pines cospliente a la nexys 4, cuando corremos "Generate Programming File" nos marca error pero en la ventana de error no nos indica cual es, en tanto a la declaración de los LEDs y Switches eso esta correcto, siento Quá en la declaración de la señal reloj algo esta mal, pero no se que es, se supone que es para la nexys 4 con artix 7 ¿Cuál podrá ser la solucion?.
## clock signal
net "clk" loc = "E3" | iostandard = "LVCMOS33";
net "clk" TNM_NET = sys_clk_pin;
timespec ts_sys_clk_pin = period sys_clk_pin 100000 khz;
## leds
net "leds<0>" loc = "T8"| iostandard = "LVCMOS33";
net "leds<1>" loc = "V9"| iostandard = "LVCMOS33";
net "leds<2>" loc = "R8"| iostandard = "LVCMOS33";
net "leds<3>" loc = "T6"| iostandard = "LVCMOS33";
net "leds<4>" loc = "T5"| iostandard = "LVCMOS33";
net "leds<5>" loc = "T4"| iostandard = "LVCMOS33";
net "leds<6>" loc = "U7"| iostandard = "LVCMOS33";
net "leds<7>" loc = "U6"| iostandard = "LVCMOS33";
## switches
net "sw<0>" loc = "U9"| iostandard = "LVCMOS33";
net "sw<1>" loc = "U8"| iostandard = "LVCMOS33";
net "sw<2>" loc = "R7"| iostandard = "LVCMOS33";
net "sw<3>" loc = "R6"| iostandard = "LVCMOS33";
net "sw<4>" loc = "R5"| iostandard = "LVCMOS33";
net "sw<5>" loc = "V7"| iostandard = "LVCMOS33";
net "sw<6>" loc = "V6"| iostandard = "LVCMOS33";
net "sw<7>" loc = "V5"| iostandard = "LVCMOS33";
Solo en la consola nos indica lo siguiente...
Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f test_kcpsm6.ut test_kcpsm6.ncd
INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most
commonly, bitgen has determined and will use a specific value instead of the
generic command-line value of "Auto". Alternately, this message appears if
the same option is specified multiple times on the command-line. In this
case, the option listed last will be used.
WARNING:Bitgen:26 - Bitgen only supports DRC but not bitstream generation on
this device. This condition can occur if there are problems obtaining a
license to run bitgen or if the design targets a device which is Early
Access.
Process "Generate Programming File" failed
Este es un proyecto para la escuela así que agradecería mucho si pudieran proporcionarme una solucion de como resolver este error, el codigo lo saque de "KCPSM6_User_Guide_30Sept14" o si me pudieran indicar donde puedo comprar la nexys 3 con spartan6 también lo agradeceríen