HDLCompiler:1731 - КОНТРОЛЛЕР СТИРАЛЬНОЙ МАШИНЫ VHDL

Question

Я пытаюсь написать язык VHDL для контроллера стиральной машины, но не могу понять причину, по которой у меня возникают ошибки при синтезе ниже:

ERROR:HDLCompiler:1731 - Line 152: found '0' definitions of operator "/", cannot determine exact overloaded matching definition for "/"

ERROR:HDLCompiler:1731 - Line 156: found '0' definitions of operator " * ", cannot determine exact overloaded matching definition for " * "

ERROR:HDLCompiler:1731 - Line 160: found '0' definitions of operator " * ", cannot determine exact overloaded matching definition for " * "

ERROR:HDLCompiler:1731 - Line 164: found '0' definitions of operator " * ", cannot determine exact overloaded matching definition for " * "

ERROR:HDLCompiler:1731 - Line 168: found '0' definitions of operator " * ", cannot determine exact overloaded matching definition for " * "

ERROR:HDLCompiler:1731 - Line 172: found '0' definitions of operator " * ", cannot determine exact overloaded matching definition for " * "

ERROR:HDLCompiler:1731 - Line 176: found '0' definitions of operator " * ", cannot determine exact overloaded matching definition for " * "

ERROR:HDLCompiler:1731 - Line 180: found '0' definitions of operator " * ", cannot determine exact overloaded matching definition for " * "

Машина запускается при хранении жетона для белья. Затем выполняется последовательность следующих этапов: замачивание - стирка - полоскание - отжим. Имеется переключатель "двойная стирка", который, если он включен, вызывает повторную стирку и полоскание. Другими словами, переключатель "двойной стирки" вызывает следующую 6-ступенчатую последовательность:

Замачивание - стирка - полоскание - стирка - полоскание - отжим

Данная ошибка относится к коду ниже:

process(reset,clk_in)
begin
    if reset='1' then
        current_state<=s0;
        i:=0;
        elsif clk_in'event and clk_in='1' then
            if i < state_time and current_state/=s7 then
                i := i + 1;
        end if;

        if current_state=s0 then
            sevenseg_timer<="1000000";
        end if;

        if current_state/=s0 and i >=0 and i <= state_time/9 then
            sevenseg_timer<= "0010000"; --9
        end if;

        if current_state/=s0 and state_time/9 and i <= (state_time/9)*2 then
            sevenseg_timer<="0000000"; --8
        end if;

        if current_state/=s0 and (state_time/9) * 2 and i <= (state_time/9)*3 then
            sevenseg_timer<= "1111000"; --7
        end if;

        if current_state/=s0 and (state_time/9) * 3 and i <= (state_time/9)*4 then
            sevenseg_timer<= "0000010"; --6
        end if;

        if current_state/=s0 and (state_time/9) * 4 and i <= (state_time/9)*5 then
            sevenseg_timer<= "0010010"; --5
        end if;

        if current_state/=s0 and (state_time/9) * 5 and i <= (state_time/9)*6 then
            sevenseg_timer<= "0011001"; --4
        end if;

        if current_state/=s0 and (state_time/9) * 6 and i <= (state_time/9)*7 then
            sevenseg_timer<= "0110000"; --3
        end if;

        if current_state=s0 and (state_time/9)* 7 and i <= (state_time/9)*8 then
            sevenseg_timer<= "0100100"; --2
        end if;

        if current_state=s0 and (state_time/9) * 8 and i <= (state_time/9)*9 then
            sevenseg_timer<= "1111001"; --1
        end if;

        if current_state = s6 and lid='1' then
            current_state <=s7;
        end if;

        if current_state = s7 and Lid='0' then
            current_state <= s6;
        end if;

        if i =state_time then
            i :=0;
            current_state<=next_state;
        end if;
    end if;
end process;

весь код можно увидеть ниже.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity VMC_VDL is
Port ( clk_in : in  STD_LOGIC;
       DW : in  STD_LOGIC;
       T : in  STD_LOGIC;
       Reset : in  STD_LOGIC;
       Soak : out  STD_LOGIC;
       Wash : out  STD_LOGIC;
       Rinse : out  STD_LOGIC;
       Spin : out  STD_LOGIC;
       Lid : in  STD_LOGIC;
       sevenseg_statenumber : out  STD_LOGIC_VECTOR (6 downto 0);
       sevenseg_timer : out  STD_LOGIC_VECTOR (6 downto 0):="1000000");


end VMC_VDL;

architecture Behavioral of VMC_VDL is
    type state_type is (s0, s1, s2, s3, s4, s5, s6, s7);
    signal current_state, next_state:state_type;
    shared variable i : integer range 0 to 50000;
    shared variable state_time : integer range 0 to 50000;
    shared variable base_time: integer := 25;

begin

process(current_state, T)
begin
case current_state is
    when s0 =>
        Soak <='0';
        Wash <= '0';
        Rinse <= '0';
        Spin <= '0';
        sevenseg_statenumber<="1111001"; --1
        state_time:=1;
        if T='1' then
            next_state<=s1;
            else next_state<=s0;
        end if;
    when s1 =>
        Soak <='1';
        Wash <= '0';
        Rinse <= '0';
        Spin <= '0';
        sevenseg_statenumber<="1111001"; --1
        state_time:=base_time*5;
        if DW='1' then
            next_state<=s2;
            else next_state<=s4;
        end if;
    when s2 =>
        Soak <='0';
        Wash <= '1';
        Rinse <= '0';
        Spin <= '0';
        sevenseg_statenumber<="0100100"; --2
        state_time:=base_time*3;
        next_state <=s3;
    when s3 =>
        Soak <='0';
        Wash <= '0';
        Rinse <= '1';
        Spin <= '0';
        sevenseg_statenumber<="0110000"; --3
        state_time:=base_time*4;
        next_state <=s4;
    when s4 =>
        Soak <='0';
        Wash <= '1';
        Rinse <= '0';
        Spin <= '0';
        sevenseg_statenumber<="0011001"; --4
        state_time:=base_time*3;
        next_state <=s5;
    when s5 =>
        Soak <='0';
        Wash <= '0';
        Rinse <= '1';
        Spin <= '0';
        sevenseg_statenumber<="0010010"; --5
        state_time:=base_time*4;
        next_state <=s6;
    when s6 =>
        Soak <='0';
        Wash <= '0';
        Rinse <= '0';
        Spin <= '1';
        sevenseg_statenumber<="0000010"; --6
        state_time:=base_time*10;
        next_state <=s0;
    when s7 =>
        Soak <='0';
        Wash <= '0';
        Rinse <= '0';
        Spin <= '0';
        sevenseg_statenumber<="1000011"; --L
        state_time:=base_time*10;
    end case;
end process;

process(reset,clk_in)
begin
    if reset='1' then
        current_state<=s0;
        i:=0;
        elsif clk_in'event and clk_in='1' then
            if i < state_time and current_state/=s7 then
                i := i + 1;
        end if;

        if current_state=s0 then
            sevenseg_timer<="1000000";
        end if;

        if current_state/=s0 and i >=0 and i <= state_time/9 then
            sevenseg_timer<= "0010000"; --9
        end if;

        if current_state/=s0 and state_time/9 and i <= (state_time/9)*2 then
            sevenseg_timer<="0000000"; --8
        end if;

        if current_state/=s0 and (state_time/9) * 2 and i <= (state_time/9)*3 then
            sevenseg_timer<= "1111000"; --7
        end if;

        if current_state/=s0 and (state_time/9) * 3 and i <= (state_time/9)*4 then
            sevenseg_timer<= "0000010"; --6
        end if;

        if current_state/=s0 and (state_time/9) * 4 and i <= (state_time/9)*5 then
            sevenseg_timer<= "0010010"; --5
        end if;

        if current_state/=s0 and (state_time/9) * 5 and i <= (state_time/9)*6 then
            sevenseg_timer<= "0011001"; --4
        end if;

        if current_state/=s0 and (state_time/9) * 6 and i <= (state_time/9)*7 then
            sevenseg_timer<= "0110000"; --3
        end if;

        if current_state=s0 and (state_time/9)* 7 and i <= (state_time/9)*8 then
            sevenseg_timer<= "0100100"; --2
        end if;

        if current_state=s0 and (state_time/9) * 8 and i <= (state_time/9)*9 then
            sevenseg_timer<= "1111001"; --1
        end if;

        if current_state = s6 and lid='1' then
            current_state <=s7;
        end if;

        if current_state = s7 and Lid='0' then
            current_state <= s6;
        end if;

        if i =state_time then
            i :=0;
            current_state<=next_state;
        end if;
    end if;
end process;




end Behavioral;

Кто-нибудь может помочь?