Сигнал подключен к следующим нескольким драйверам в VHDL
Я хочу вывести какое-то значение (в этом примере теста сигнала) на led2 (первые восемь светодиодов), но получаю следующую ошибку:
Signal out_port_reg_01[7] in unit pb_nexys_a7 is connected to following multiple drivers:
Driver 0: output signal out_port_reg_01[7] of instance Flip-flop (out_port_reg_01).
Driver 1: output signal out_port_reg_01[7] of instance Flip-flop (_i000063).
Driver 0: output signal out_port_reg_01[6] of instance Flip-flop (out_port_reg_01).
Driver 1: output signal out_port_reg_01[6] of instance Flip-flop (_i000063).
Driver 0: output signal out_port_reg_01[5] of instance Flip-flop (out_port_reg_01).
Driver 1: output signal out_port_reg_01[5] of instance Flip-flop (_i000063).
Driver 0: output signal out_port_reg_01[4] of instance Flip-flop (out_port_reg_01).
Driver 1: output signal out_port_reg_01[4] of instance Flip-flop (_i000063).
Driver 0: output signal out_port_reg_01[3] of instance Flip-flop (out_port_reg_01).
Driver 1: output signal out_port_reg_01[3] of instance Flip-flop (_i000063).
Driver 0: output signal out_port_reg_01[2] of instance Flip-flop (out_port_reg_01).
Driver 1: output signal out_port_reg_01[2] of instance Flip-flop (_i000063).
Driver 0: output signal out_port_reg_01[1] of instance Flip-flop (out_port_reg_01).
Driver 1: output signal out_port_reg_01[1] of instance Flip-flop (_i000063).
Driver 0: output signal out_port_reg_01[0] of instance Flip-flop (out_port_reg_01).
Driver 1: output signal out_port_reg_01[0] of instance Flip-flop (_i000063).
Это для проекта, поэтому я должен вывести значение через out_port_reg_01, я не могу использовать светодиод (7 вниз до 0), даже если он будет работать. Вот код ниже:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pb_nexys_a7 is
port(
clk : in std_logic := '0';
btn_rst : in std_logic := '0';
rgb : out std_logic_vector(5 downto 0) := "00000";
led : out std_logic_vector(15 downto 0) := "0000000000000000";
sw : in std_logic_vector(15 downto 0) := "0000000000000000";
btn : in std_logic_vector(4 downto 0) := "00000";
hex_sel : out std_logic_vector(7 downto 0) := "00000000";
hex_seg : out std_logic_vector(7 downto 0) := "00000000";
u_rx : in std_logic := '0';
u_tx : out std_logic := '0'
-- u_cts : out std_logic := '0'
-- u_rts : in std_logic := '0'
);
end pb_nexys_a7;
architecture Behavioral of pb_nexys_a7 is
-- processor hex_seld program memory
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal in_port : std_logic_vector(7 downto 0) := "00000000";
signal out_port : std_logic_vector(7 downto 0) := "00000000";
signal port_id : std_logic_vector(7 downto 0) := "00000000";
signal bram_enable : std_logic := '0';
signal write_strobe : std_logic := '0';
signal k_write_strobe : std_logic := '0';
signal read_strobe : std_logic := '0';
signal kcpsm6_reset : std_logic := '0';
signal rdl : std_logic := '0';
signal int_ack : std_logic := '0';
signal sleep : std_logic := '0';
component kcpsm6 generic(
hwbuild : std_logic_vector(7 downto 0) := X"75";
interrupt_vector : std_logic_vector(11 downto 0) := X"7FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component program generic(
C_FAMILY : string := "7S";
C_RAM_SIZE_KWORDS : integer := 2;
C_JTAG_LOADER_ENABLE : integer := 1);
port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
component uart_tx6 Port (
data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
component uart_rx6 Port (
serial_in : in std_logic;
en_16_x_baud : in std_logic;
data_out : out std_logic_vector(7 downto 0);
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
-- output port
signal out_port_reg_00 : std_logic_vector(7 downto 0) := "00000000";
signal out_port_reg_01 : std_logic_vector(7 downto 0) := "00000000";
signal out_port_reg_02 : std_logic_vector(7 downto 0) := "00000000";
signal out_port_reg_03 : std_logic_vector(7 downto 0) := "00000000";
signal out_port_reg_04 : std_logic_vector(7 downto 0) := "00000000";
signal out_port_reg_05 : std_logic_vector(7 downto 0) := "00000000";
signal out_port_reg_06 : std_logic_vector(7 downto 0) := "00000000";
signal out_port_reg_07 : std_logic_vector(7 downto 0) := "00000000";
signal out_port_reg_08 : std_logic_vector(7 downto 0) := "00000000";
signal out_port_reg_09 : std_logic_vector(7 downto 0) := "00000000";
-- signal out_port_reg_10 : std_logic_vector(7 downto 0) := "00000000";
-- signal out_port_reg_11 : std_logic_vector(7 downto 0) := "00000000";
-- signal out_port_reg_12 : std_logic_vector(7 downto 0) := "00000000";
-- signal out_port_reg_13 : std_logic_vector(7 downto 0) := "00000000";
-- signal out_port_reg_14 : std_logic_vector(7 downto 0) := "00000000";
-- signal out_port_reg_15 : std_logic_vector(7 downto 0) := "00000000";
-- input port
signal in_port_reg_00 : std_logic_vector(7 downto 0) := "00000000";
signal in_port_reg_01 : std_logic_vector(7 downto 0) := "00000000";
signal in_port_reg_02 : std_logic_vector(7 downto 0) := "00000000";
signal in_port_reg_03 : std_logic_vector(7 downto 0) := "00000000";
signal in_port_reg_04 : std_logic_vector(7 downto 0) := "00000000";
-- signal in_port_reg_05 : std_logic_vector(7 downto 0) := "00000000";
-- signal in_port_reg_06 : std_logic_vector(7 downto 0) := "00000000";
-- signal in_port_reg_07 : std_logic_vector(7 downto 0) := "00000000";
signal btn_reg : std_logic_vector(4 downto 0) := "00000";
alias btn_int : std_logic is btn_reg(4);
alias led1 : std_logic_vector(7 downto 0) is led(15 downto 8);
alias led2 : std_logic_vector(7 downto 0) is led( 7 downto 0);
signal rgb1 : std_logic_vector(7 downto 0) := "00000000";
signal rgb2 : std_logic_vector(7 downto 0) := "00000000";
signal u_status : std_logic_vector(5 downto 0) := "000000";
signal rx_data_reg : std_logic_vector(7 downto 0) := "00000000";
signal rx_data_out : std_logic_vector(7 downto 0) := "00000000";
signal tx_data_in : std_logic_vector(7 downto 0) := "00000000";
signal u_reset : std_logic_vector(1 downto 0) := "00";
-- baud rate calculator
signal baud_count : integer range 0 to 53 := 0;
signal en_16_x_baud : std_logic := '0';
-- uart rx hex_seld tx
signal read_u_rx : std_logic := '0'; -- read from rx
signal write_u_tx : std_logic := '0'; -- write to tx
signal u_rx_r : std_logic := '0'; -- rx buffer reset
signal u_tx_r : std_logic := '0'; -- tx buffer reset
-- hex decoder
component hex_decoder is
port( clk : in STD_LOGIC;
hex1 : in STD_LOGIC_VECTOR(7 downto 0);
hex2 : in STD_LOGIC_VECTOR(7 downto 0);
hex3 : in STD_LOGIC_VECTOR(7 downto 0);
hex4 : in STD_LOGIC_VECTOR(7 downto 0);
sel : out STD_LOGIC_VECTOR(7 downto 0);
seg : out STD_LOGIC_VECTOR(7 downto 0));
end component;
signal hex1 : std_logic_vector(7 downto 0) := "00000111";
signal hex2 : std_logic_vector(7 downto 0) := "00000011";
signal hex3 : std_logic_vector(7 downto 0) := "00000001";
signal hex4 : std_logic_vector(7 downto 0) := "00000101";
-- debouncer
component debounce is
generic ( delay : integer := 10_000);
Port ( clk : in STD_LOGIC := '0';
rst : in STD_LOGIC := '0';
s_in : in STD_LOGIC := '0';
s_out : out STD_LOGIC);
end component;
signal test: std_logic_vector(7 downto 0):="00011101";
begin
-------------------------------------------------------------------------------------------------------------------
-- processor, program memory, interrupt
processor: kcpsm6
generic map ( hwbuild => X"FF",
interrupt_vector => X"7FF",
scratch_pad_memory_size => 64)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => btn_int,
interrupt_ack => int_ack, -- not used
sleep => '0', -- not used
reset => kcpsm6_reset,
clk => clk );
program_rom: program generic map(
C_FAMILY => "7S",
C_RAM_SIZE_KWORDS => 2,
C_JTAG_LOADER_ENABLE => 1)
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => rdl,
clk => clk);
kcpsm6_reset <= (not btn_rst) or rdl; -- external or internal reset
-------------------------------------------------------------------------------------------------------------------
-- output port decoder
process(clk)
begin
if clk'event and clk = '1' then
if kcpsm6_reset='1' then
out_port_reg_00 <= (others =>'0');
out_port_reg_01 <= (others =>'0');
out_port_reg_02 <= (others =>'0');
out_port_reg_03 <= (others =>'0');
out_port_reg_04 <= (others =>'0');
out_port_reg_05 <= (others =>'0');
out_port_reg_06 <= (others =>'0');
out_port_reg_07 <= (others =>'0');
out_port_reg_08 <= (others =>'0');
out_port_reg_09 <= (others =>'0');
elsif write_strobe = '1' or k_write_strobe = '1' then
if port_id(3 downto 0) = "0000" then out_port_reg_00 <= out_port; end if;
if port_id(3 downto 0) = "0001" then out_port_reg_01 <= out_port; end if;
if port_id(3 downto 0) = "0010" then out_port_reg_02 <= out_port; end if;
if port_id(3 downto 0) = "0011" then out_port_reg_03 <= out_port; end if;
if port_id(3 downto 0) = "0100" then out_port_reg_04 <= out_port; end if;
if port_id(3 downto 0) = "0101" then out_port_reg_05 <= out_port; end if;
if port_id(3 downto 0) = "0110" then out_port_reg_06 <= out_port; end if;
if port_id(3 downto 0) = "0111" then out_port_reg_07 <= out_port; end if;
if port_id(3 downto 0) = "1000" then out_port_reg_08 <= out_port; end if;
if port_id(3 downto 0) = "1001" then out_port_reg_09 <= out_port; end if;
-- if port_id(3 downto 0) = "1010" then out_port_reg_10 <= out_port; end if;
-- if port_id(3 downto 0) = "1011" then out_port_reg_11 <= out_port; end if;
-- if port_id(3 downto 0) = "1100" then out_port_reg_12 <= out_port; end if;
-- if port_id(3 downto 0) = "1101" then out_port_reg_13 <= out_port; end if;
-- if port_id(3 downto 0) = "1110" then out_port_reg_14 <= out_port; end if;
-- if port_id(3 downto 0) = "1111" then out_port_reg_15 <= out_port; end if;
end if;
end if;
end process;
led1 <= out_port_reg_00;
led2 <= out_port_reg_01;
hex1 <= out_port_reg_02;
hex2 <= out_port_reg_03;
hex3 <= out_port_reg_04;
hex4 <= out_port_reg_05;
rgb2 <= out_port_reg_06;
rgb1 <= out_port_reg_07;
tx_data_in <= out_port_reg_08;
u_reset <= out_port_reg_09(1 downto 0);
hex: hex_decoder port map(clk,hex1,hex2,hex3,hex4,hex_sel,hex_seg);
rgb <= rgb2(2) & rgb2(1) & rgb2(0) & rgb1(2) & rgb1(1) & rgb1(0);
-- rgb: rgb_pwm port map(clk,rgb1,rgb2,rgb);
-------------------------------------------------------------------------------------------------------------------
-- input port decoder
process(clk)
begin
if clk'event and clk = '1' then
out_port_reg_01<=test;
in_port_reg_00 <= sw(15 downto 8);
in_port_reg_01 <= sw( 7 downto 0);
in_port_reg_02 <= "000" & btn_reg;
in_port_reg_03 <= "00" & u_status;
in_port_reg_04 <= rx_data_out;
-- in_port_reg_05 <= ...
-- in_port_reg_06 <= ...
-- in_port_reg_07 <= ...
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
case port_id(2 downto 0) is
when "000" => in_port <= in_port_reg_00;
when "001" => in_port <= in_port_reg_01;
when "010" => in_port <= in_port_reg_02;
when "011" => in_port <= in_port_reg_03;
when "100" => in_port <= in_port_reg_04;
-- when "101" => in_port <= in_port_reg_05;
-- when "110" => in_port <= in_port_reg_06;
-- when "111" => in_port <= in_port_reg_07;
when others => in_port <= (others => 'X');
end case;
end if;
end process;
-------------------------------------------------------------------------------------------------------------------
-- uart stuff
process(clk)
begin
if clk'event and clk = '1' then
if baud_count >= 53 then -- 53 baudrate 115200
baud_count <= 0;
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
en_16_x_baud <= '0';
end if;
end if;
end process;
tx: uart_tx6 port map (
data_in => tx_data_in,
en_16_x_baud => en_16_x_baud,
serial_out => u_tx,
buffer_write => write_u_tx,
buffer_data_present => u_status(0),
buffer_half_full => u_status(1),
buffer_full => u_status(2),
buffer_reset => u_tx_r,
clk => clk);
rx: uart_rx6 port map (
serial_in => u_rx,
en_16_x_baud => en_16_x_baud,
data_out => rx_data_out,
buffer_read => read_u_rx,
buffer_data_present => u_status(3),
buffer_half_full => u_status(4),
buffer_full => u_status(5),
buffer_reset => u_rx_r,
clk => clk);
u_tx_r <= kcpsm6_reset or u_reset(0); -- reset uart tx buffer
u_rx_r <= kcpsm6_reset or u_reset(1); -- reset uart rx buffer
process(clk)
begin
if clk'event and clk='1' then
if read_strobe = '1' then
if port_id(3 downto 0) = "0100" then
read_u_rx <= '1';
else
read_u_rx <= '0';
end if;
else
read_u_rx <= '0';
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if k_write_strobe = '1' or write_strobe = '1' then
if port_id(3 downto 0) = "1000" then
write_u_tx <= '1';
else
write_u_tx <= '0';
end if;
else
write_u_tx <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------------------
-- debounce buttons -----------------------------------------------------------------------------------------------
--
-- |_|4.
--
-- |_|2. |_|0. |_|3.
--
-- |_|1.
--
debounce0: debounce port map(clk,kcpsm6_reset,btn(0),btn_reg(4));
debounce1: debounce port map(clk,kcpsm6_reset,btn(1),btn_reg(3));
debounce2: debounce port map(clk,kcpsm6_reset,btn(2),btn_reg(2));
debounce3: debounce port map(clk,kcpsm6_reset,btn(3),btn_reg(0));
debounce4: debounce port map(clk,kcpsm6_reset,btn(4),btn_reg(1));
-------------------------------------------------------------------------------------------------------------------
end Behavioral;
Я нашел много сообщений с этим вопросом, но ни один из них мне не помог. Я пробовал несколько решений, но ни одно из них не помогло. Спасибо за помощь