Пример RFNoC завершается неудачно, модуль ошибки ddr3_32bit не найден
Я пытаюсь запрограммировать USRP x310 с примером для RFNoC 4 .
Проблема возникает, когда я добираюсь до
make gain_x310_rfnoc_image_core
Через несколько минут появляется следующее сообщение об ошибке:
BUILDER: Releasing IP location: /home/user/Documents/git/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/aurora_64b66b_pcs_pma
Using parser configuration from: /home/user/Documents/git/uhd/fpga/usrp3/top/x300/dev_config.json
[00:00:00] Executing command: vivado -mode batch -source /home/user/Documents/git/uhd/fpga/usrp3/top/x300/build_x300.tcl -log build.log -journal x300.jou
CRITICAL WARNING: [filemgmt 20-1440] File '/home/user/Documents/git/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v' already exists in the project as a part of sub-design file '/home/user/Documents/git/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci'. Explicitly adding the file outside the scope of the sub-design can lead to unintended behaviors and is not recommended.
[00:00:14] Current task: Initialization +++ Current Phase: Starting
[00:00:14] Current task: Initialization +++ Current Phase: Finished
[00:00:14] Executing Tcl: synth_design -top x300 -part xc7k410tffg900-2 -verilog_define BUILD_1G=1 -verilog_define BUILD_10G=1 -verilog_define SFP0_1GBE=1 -verilog_define SFP1_10GBE=1 -verilog_define X310=1 -verilog_define GIT_HASH=32'hfe520e3f -verilog_define RFNOC_EDGE_TBL_FILE=/home/user/Documents/rfnoc-example/rfnoc/icores/x310_static_router.hex
[00:00:14] Starting Synthesis Command
ERROR: [Synth 8-439] module 'ddr3_32bit' not found [/home/user/Documents/git/uhd/fpga/usrp3/top/x300/x300.v:1195]
ERROR: [Synth 8-6156] failed synthesizing module 'x300' [/home/user/Documents/git/uhd/fpga/usrp3/top/x300/x300.v:20]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
[00:02:21] Current task: Synthesis +++ Current Phase: Starting
[00:02:21] Current task: Synthesis +++ Current Phase: Finished
[00:02:21] Process terminated. Status: Failure
========================================================
Warnings: 87
Critical Warnings: 1
Errors: 3
make[5]: *** [Makefile.x300.inc:127: bin] Error 1
make[4]: *** [Makefile:85: X310_HG] Error 2
Built target gain_x310_rfnoc_image_core
У меня Vivado, как обычно, установлен в другом каталоге, поэтому я изменил файл uhd / fpga / usrp3 / top / x300 / setupenv.sh, включив в него путь:
source $REPO_BASE_PATH/tools/scripts/setupenv_base.sh --vivado-path=/home/user/tools/Xilinx/Vivado
Обнаружил аналогичную проблему при поиске решения. В этом случае было рекомендовано переключиться на ветку UHD-3.15.LTS , но я использую ветвь UHD-4.0, как описано в примере.