FSM в Verilog некорректно компилируется с помощью quartus

Question

Мой FSM выдаст мне все правильные выходы при моделировании, но когда я собираюсь поставить его на DE0-CV, светодиодный индикатор работает правильно, но 7-сегментный дисплей не меняет состояния. Я не совсем уверен, как включить HEX дисплей со светодиодным дисплеем. Я новичок в Verilog и начинающий программист в целом, поэтому любая помощь очень ценится.
FSM_pv для FPGA, а FSM - просто модуль моделирования

//////////FSM_fpga
    module FSM_pv(input KEY0, SW0, SW1, SW2, SW3, SW4,
            output [6:0] HEX0, HEX1, HEX2, HEX3, output reg [4:0] LED_SW);
    FSM fsm1(state,Z,KEY0,SW0,SW1,SW2,SW3,SW4);
    always @ (*) begin
        if (SW0)
            LED_SW = 5'b00001;
        else if (SW1)
            LED_SW = 5'b00010;
        else if (SW2)
            LED_SW = 5'b00100;
        else if (SW3)
            LED_SW = 5'b01000;
        else if (SW4)
            LED_SW = 5'b10000;      
        else
            LED_SW = 5'b00000;
        end
    ASCIICodes ascii(state, HEX3, HEX2, HEX1, HEX0);
    endmodule

    ///////////
    //ASCII
    module ASCIICodes(input [2:0] state, output [6:0] HexSeg3, HexSeg2, HexSeg1, HexSeg0);
       reg [7:0] Message [3:0];
       always @ (*) begin
          case (state)
        3'b000 : begin 
            Message[3] = "A";
            Message[2] = "B";
            Message[1] = "C";
            Message[0] = "D";
                end
            3'b001 : begin
            Message[3] = "S";
            Message[2] = "_";
            Message[1] = "0";
            Message[0] = "1";
                end
        3'b010 : begin
            Message[3] = "S";
            Message[2] = "_";
            Message[1] = "0";
            Message[0] = "2";
            end
        3'b011 : begin
            Message[3] = "S";
            Message[2] = "_";
            Message[1] = "0";
            Message[0] = "3";
            end
        3'b100 : begin
            Message[3] = "S";
            Message[2] = "_";
            Message[1] = "0";
            Message[0] = "4";
            end
        endcase
    end 
    ASCII27Seg SevH3 (Message[3], HexSeg3);
    ASCII27Seg SevH2 (Message[2], HexSeg2);
    ASCII27Seg SevH1 (Message[1], HexSeg1);
    ASCII27Seg SevH0 (Message[0], HexSeg0);
    endmodule

    ///////
    //FSM
    module FSM(output reg [2:0] state, output reg [1:0] Z, input KEY0,SW0,SW1,SW2,SW3,SW4);
    reg [2:0] nextQ;
    localparam Strt=3'b000, Seen1=3'b001, Seen12=3'b010, Seen123=3'b011, Seen1234=3'b100;
    always @ (posedge KEY0 or posedge SW0)
        if (SW0)
           state <= Strt;
        else
           state <= nextQ;
    //initialize values
    initial begin
        nextQ=3'b000;
        state=3'b000;
    end 
    always @(*) begin
        nextQ = state;
        Z = 2'b00;
        case (state)
            Strt :
            if (SW1 & ~SW2 &~SW3 & ~SW4)
               nextQ = Seen1;
            else
               nextQ = Strt;
            Seen1:
            if (~SW1 & SW2 &~SW3 & ~SW4)
               nextQ = Seen12;
            else
               nextQ = Seen1;
            Seen12: begin
            Z=2'b11;
            if (~SW1 & ~SW2 & SW3 & ~SW4)
               nextQ = Seen123;
            else if (SW4)
               nextQ = Seen1;
            else
               nextQ = Seen12;
            end
            Seen123: begin
            Z=2'b01;
            if (~SW1 & SW2 &~SW3 & ~SW4)
               nextQ = Seen1;
            else if (~SW1 & ~SW2 &~SW3 & SW4)
               nextQ = Seen1234;        
            else
               nextQ = Seen123;
            end
            Seen1234: begin
            Z=2'b10;
            if (SW1 & ~SW2 &~SW3 & ~SW4)
               nextQ = Seen1;
            else if (~SW1 & ~SW2 &~SW3 & SW4)
               nextQ = Strt;
            else
               nextQ = Seen1234;
            end
    //set default
        default : nextQ = Strt;
        endcase
    end
    endmodule

    ////////
    //FSM_tb
    `timescale 1ns/1ps
    module FSM_tb();
    wire [2:0] state;
    wire [1:0] Z;
    reg KEY0,SW0,SW1,SW2,SW3,SW4;
    FSM fsm1 (state, Z, KEY0, SW0, SW1, SW2, SW3, SW4);
    initial begin
    // first test sequence 
        SW0=0; SW1=0; SW2=0; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=1; SW1=0; SW2=0; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=1; SW2=0; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=1; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=0; SW3=1; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=1; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=1; SW1=0; SW2=0; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
    // reset for next sequence
        SW0=0; SW1=0; SW2=0; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #50;
    // next test sequence
        SW0=1; SW1=0; SW2=0; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=1; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=1; SW2=0; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=1; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=0; SW3=0; SW4=1; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=1; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=0; SW3=1; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=1; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=1; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=0; SW3=1; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=0; SW3=0; SW4=1; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=1; SW2=0; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=1; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=0; SW3=1; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=0; SW3=0; SW4=1; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=1; SW2=0; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=1; SW3=0; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=0; SW3=1; SW4=0; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=0; SW3=0; SW4=1; KEY0=1; #10;
        KEY0=0; #10;
        SW0=0; SW1=0; SW2=0; SW3=0; SW4=1; KEY0=1; #10;
        KEY0=0; #10;
    end

    endmodule